`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/07 10:16:36
// Design Name: 
// Module Name: pulse_jk_flipflop
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pulse_jk_flipflop(
input sw3_CLK,
input sw2_J,
input sw1_K,
output led8_Q);
wire s1_m,s2_m,s1_s,s2_s,temp_out1,temp_out2,temp_q;
assign s1_m=!(sw2_J &sw3_CLK & temp_q);
assign s2_m=!(sw1_K &sw3_CLK & led8_Q);
assign s1_s=!(!sw3_CLK & temp_out1);
assign s2_s=!(!sw3_CLK & temp_out2);
nand_rs_latch   nand_rs_latch_m(.s1(s1_m),.s2(s2_m),.Q1(temp_out1),.Q2(temp_out2));
nand_rs_latch   nand_rs_latch_s(.s1(s1_s),.s2(s2_s),.Q1(led8_Q),.Q2(temp_q));
endmodule
